Espressif Systems /ESP32-H2 /DMA /OUT_INT_RAW_CH1

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Interpret as OUT_INT_RAW_CH1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OUT_DONE)OUT_DONE 0 (OUT_EOF)OUT_EOF 0 (OUT_DSCR_ERR)OUT_DSCR_ERR 0 (OUT_TOTAL_EOF)OUT_TOTAL_EOF 0 (OUTFIFO_OVF)OUTFIFO_OVF 0 (OUTFIFO_UDF)OUTFIFO_UDF

Description

Raw status interrupt of channel 0

Fields

OUT_DONE

The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.

OUT_EOF

The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.

OUT_DSCR_ERR

The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0.

OUT_TOTAL_EOF

The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.

OUTFIFO_OVF

This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.

OUTFIFO_UDF

This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.

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